Servers with new Xeon E5 chips base on the Sandy Bridge microarchitecture will become useable early next twelvemonth , Intel officials say on Tuesday .

The E5 silicon chip will have up to eight processing gist and be capable to run 16 threads per socket , said Kirk Skaugen , frailty president and general director of Intel ’s Data Center Group , at the Intel Developer Forum in San Francisco . The chip has already started shipping in bulk and will deliver significantly eminent execution than current Xeon chip , Skaugen said .

“ This is the most phenomenal chip we ’ve deliver on Intel to the server market , ” Skaugen said .

The chip is targeted at high - carrying out computing and cloud supplier , Skaugen enounce . The Xeon E5 will succeed the Xeon 5600 chips , which were released around the center of last year and were based on the Westmere architecture . Apple ’s current Mac Pro lineup include a received configuration power by a pair of quadrangle - meat 2.4GHZ Xeon E5620 Westmere processors .

Intel is aim the chip at servers with between two and four socket . Intel already offers low - conclusion Xeon E3 potato chip based on the Sandy Bridge microarchitecture for servers with up to two socket . The society also offers Xeon E7 chips , based on the one-time Westmere architecture , with up to 10 gist for servers with more than four sockets .

Intel has 400 server blueprint wins already for the chip , which is almost double that of the Xeon 5500 chips that were released in 2009 , Skaugen say . The chip will compete with new server chips base on the Bulldozer microarchitecture from Advanced Micro Devices . AMD originally this calendar month said it had startle shipping its 16 - core Interlagos chip shot to server manufacturer , who would release production in the 4th quarter .

The chip also bluster some chip enhancements for Intel . This is the first time Intel will integrate the PCI - Express autobus in the microprocessor , Skaugen said . That will improve data throughput inside servers while saving power .

Intel did not share further detail about the E5 chip such as clock velocity , hoard or backward socket compatibility . Further details about the chip shot will come at a later date , an Intel spokesman said .

Skaugen also reiterate the company ’s committal to the Itanium splintering , saying it will be able to co - exist with Xeon crisp , and the dispute between the two was mainly about operating systems .

Xeon and Itanium chips have many uncouth wrongdoing - correction and RAS ( reliability , handiness and serviceableness ) feature demanded by high - remainder servers , but are base on different architecture . Itanium is designed for mainframe operating organization and Unix flavors such as Hewlett - Packard ’s HP - UX , while Xeon chips could mould with Windows , Linux and Sun ’s SPARC environs , Skaugen aver .

“ There ’s no workload in the world that can not run on Xeon processors , ” Skaugen allege .

While Skaugen plugged Xeon , he also sound out that the next Itanium poker chip , code - name Poulson , would deliver double the carrying into action of current Itanium chip and be in production next year .

IDF will run through Thursday in San Francisco ’s Moscone Convention Center .