An experimental Intel chip show the feasibility of ramp up central processing unit with 1000 cores , an Intel research worker has asserted .
The architecture for theIntel 48 - core Single Chip Cloud Computer(SCC ) processor is “ willy-nilly scalable , ” said Intel investigator Timothy Mattson , during a talk at the Supercomputer 2010 conference being held this workweek in New Orleans .
“ This is an architecture that could , in principle , graduated table to 1000 cores , ” he say . ” I can just keep adding , adding , adding core . ”
Only after 1000 essence or so , the diam of the meshing , or the on - chip internet connecting the many cores , will grow to such an extent that it would negatively bear on performance , Mattson said .
Intel stay adamantine that the future progress of microprocessor will calculate on packing ever more cores onto a chip . As more cores are added , however , Intel designers must face the job of scalability .
Initial multicore Saratoga chip architecture count on a set of protocols that assures that each core has the same purview of the system ’s remembering , a proficiency called stash coherency .
As more cores are tot to chips , this approach becomes problematic insofar that “ the communications protocol overhead per marrow grows with the routine of marrow , contribute to a ‘ cohesiveness wall ’ beyond which the overhead exceeds the economic value of adding cores , ” the paper accompanying Mattson ’s public lecture note .
Mattsonhas arguedthat a better access would be to eliminate cache coherency and instead let cores to pass messages among one another .
The recent work of the design team has concentrate on arise message - eliminate proficiency for the chip that would scale as more heart and soul are add .
Designed by Intel ’s TeraScale Research Program over the past several years , the chip itself is an experimental one and is not on the Intel product road map , Mattson say . A circumscribed act of copy have been circularize to research worker and developer so they can build up ontogenesis cock for the design .
The chip , first fabricated with a 45 - nanometer process at Intel facility about a year ago , is in reality a six - by - four array of tile , each tile containing two inwardness . It has more than 1.3 billion junction transistor and consumes from 25 to 125 Watt .
For simplicity ’s sake , the team used an off - the - shelf 1994 - era Pentium processor intent for the core themselves . “ Performance on this chip is not interesting , ” Mattson said . It utilise a standard x86 pedagogy solidifying .
The novelty of this CPU is in its tile computer architecture and the web and name and address infrastructure . Each magnetic core has a “ mesh interface component ” that packages information into packet and connects to an on - dining table router . Each tile also has a “ message - passing pilot , ” with 16 kilobyte of random access memory .
The team has tried various approaches to streamline the power of the processor to go past messages among the many cores .
By establish the TCP / IP communications protocol on the data connexion stratum , the team was able to course a separate Linux - free-base operating system on each heart and soul . Mattson noted that while it would be possible to run a 48 - node Linux clump on the chip , it “ would be boring . ”
“ To make this interesting , I would have to ask , how would the scheduling models map onto the unequaled feature of this cow chip , ” he said .
The team also acquire a minor API ( software programming interface ) library for message passing among the cores , called RCCE , and which Mattson pronounced as “ Rocky . ”
In test , the squad showed that substance passing among the cores could be just as speedy using RCCE as with TCP / IP - based Linux clump . And both approaches bode well for the content - blow over approach shot for inter - core communication .
“ Our preliminary work has demonstrated that the SCC mainframe and its aboriginal message passing API provide an effective software ontogeny platform , ” the newspaper publisher concludes . “ The expected difficulties due to the lack of asynchronous subject matter passing have so far not materialized . ”
In accession to talking about the poker chip ’s message - excrete capabilities , Mattson also elaborated on SCC’spower - saving capableness . The frequency of each tile can be wide-ranging . hook are provided for programmers that would allow their programs to adapt the frequency upper and even the voltage of the nitty-gritty they are endure upon . This characteristic will , however , make a newfangled challenge for software engineer , he warned .
“ It ’s a lot harder than you ’d think to face at your plan and recall ‘ how many volts do I really need ? ' ” he said .
[ Joab Jackson covers enterprise software and general applied science breaking news show for The IDG News Service . ]
