Advanced Micro Devices and IBM have added two new form of strained Si to their collectively developed 65 - nanometer chip - cause technology , which should improve the performance and reduce the power intake of future processors , the companies are require to herald Tuesday .

AMD and IBM will break the latest fruits of their collaborative effort at the International Electron Devices Meeting ( IEDM ) , in Washington , D.C. , said Gary Bronner , a grand engineer with IBM . The companies developed 65 - nanometer fabrication engineering at IBM ’s wafer lying plant in East Fishkill , New York .

Future processors from both company will use transistor that have been stretched in some agency , or pack together in others , to increase the amphetamine at which electron travel , read Nick Kepler , vice president of logic technology growth at AMD . The new methods build upon strained silicon techniques the company introduced last class at the IEDM and implement in chips earlier this year , he sound out .

For class , chip companies have build up faster transistors just by reducing the size of those junction transistor , a process live as grading , every two or so years . However , transistors are now getting so diminished that other method acting beyond wide-eyed scaling are required to improve chip performance on the schedule expected by ironware vendors and users .

One of those method acting is name laboured silicon . When certain materials are laid atop the Si substratum on which transistors are make , the atoms in those substances align with each other , compressing or stretching the silicon . confident transistor operate better when they have been compressed , while negative electronic transistor benefit from being stretched . IBM and AMD insert Dual Stress Liner technology last year that allowed both type of song to survive side - by - side on a chip .

The companies have break two young methods of straining junction transistor that progress on the Dual Stress Liner ( DSL ) technique to improve the performance of 65 nm processors , enjoin John Pellerin , managing director of logical system technology growth at IBM . The label of 65 nm manufacture technology corresponds to the mediocre size of features on the bit , in this case a step-down from the current 90 nm contemporaries of flake - make engineering .

The first method , known as stress memorization technology , improves the performance of negative transistors by adding a thin flick of silicon nitride to a disconfirming junction transistor , causing the speck to move , and then removing that film , Pellerin said . The atoms “ con ” their position and outride in place after the moving picture is removed , hence the name , he said .

The second method involves adding silicon germanium to overconfident transistors , Bronner said . The atomic number 14 germanium is essentially develop right next to the transistor logic gate , compressing that channel . The companies used to consider silicon germanium a unmanageable material to use in gamey - bulk chip shot manufacturing , but they became wonted to the use of the stuff during their collaboration , he said .

After applying the first two method , the DSL method acting is added . This involves layer a Modern compressive celluloid of silicon nitride to the chip and remove it from just the negative transistors , and then layer a tensile tenor atop the full microprocessor chip and slay it from just the positivist transistors . compare with the current generation of AMD micro chip , the 65 nm chips with all four methods apply get a 20 pct execution gain , the company said .

AMD and IBM will continue to use silicon - on - insulator , or SOI , wafers for their 65 nm chips , Kepler say . SOI wafers have a layer of silicon oxide go for to the wafer before transistors are built , which adds an insulating bed against current leak .

AMD design to take off make 65 nm chips with all four strain methods in the 2nd half of 2006 at its new Fab 36 in Dresden , Germany , Kepler said . But first , the caller will introduce the four methods into 90 nm chips made at Fab 30 in Dresden , allowing AMD to derive experience working with the newfangled method at production loudness before introducing them with the 65 nm chips , he said .

The two companies have worked together for several years on modern chip - establish technologies and recently extended their agreement through 2011 , which should take both companies through the 22 nanometre manufacture generation .

AMD and IBM have pooled their resources to compete against Intel , which has already started manufacturing 65 nm processors at its chip - crap plant life in Hillsboro , Oregon . Intel — which will become the sole supplier of the processors power Apple computers in 2006 — also is using strained silicon on its 65 nm chips .